When floorplanning data path directions of a system, one of the objectives is to provide a physically unobstructed throughput flow through a device such as a printed circuit board (PCB). For a wireless communication system, one of the objectives is to provide data flows in opposite directions without degrading performance. For a radio communication system, the data path is typically bi-directional between a network and a radio frequency (RF) transceiver and corresponding antenna(s). This bi-directional data path provides uplink data from the RF transceiver to the network and provides downlink data from the network to the RF transceiver. Further, the incessant demand for higher data throughput and the processing complexity of converting between divergent communication systems such as Ethernet, Common Public Radio Interface (CPRI), 2G, 3G and 4G communication systems such as Long Term Evolution (LTE), Universal Mobile Terrestrial System (UMTS), 5G communication systems such as LTE-NX, and the like continue to increase the processing requirements of the system. Also, the addition of new technologies such as antenna arrays and antenna beamforming techniques also increase the processing requirements of the system.
In conventional systems, an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA) typically processes a data flow in one direction only (e.g., uni-directional). With the addition of another ASIC or FPGA, the system processes data flows in multi-directions (e.g., bi-directional). Further, each ASIC or FPGA may be packaged in a discrete package, which may be rotated in relation to another ASIC or FPGA package to improve the data flows through a PCB. As ASIC processing technology continues to advance, more processing performance can be obtained from one ASIC or FPGA die. Further, as geometries in semiconductor processing continue to shrink, the ability to include multiple ASIC or FPGA dice into a single package becomes more achievable and cost effective. Also, the use of the same type of ASIC or FPGA die for multi-directional signal processing may provide certain advantages since only one architecture needs to be developed and qualified. However, one of the problems with having the same type of die in a package is that the data paths within the package become uni-directional, which may be resolved by performing more complicated routing on a PCB. Another technique is to mount one die rotated by one hundred and eighty degrees (180°) relative to the other die. However, a control flow of each die may cause congestion in the package.
US2006/0060954 describes a multichip module comprising semiconductor chips on a support medium wherein at least one second semiconductor chip includes an arrangement of contact areas which is mirror-inverted in relation to a first semiconductor chip.
US2016/0012879 describes a multi channel semiconductor device having multi dies. First and second dies may be disposed in a mirror die form and be packaged in a single package.
The Background section of this document is provided to place embodiments of the present disclosure in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.